FIG. 13 is a circuit diagram of a three-level inverter of the prior art, which converts direct current into alternating current.
In FIG. 13, the drawing symbols 51 and 52 denote DC power supplies connected in series, the positive and negative electrode potentials are denoted by P and N respectively, and the neutral point potential is denoted by M. When the DC power supplies 51 and 52 are configured from an AC power supply system, the configuration can use diode rectifiers, large-capacitance electrolytic capacitors and similar which are not shown.
Between the positive electrode potential P and the negative electrode potential N are connected series-connected circuits, of insulated-gate bipolar transistors (hereafter “IGBTs”) with antiparallel-connected diodes, for three phases. That is, a series-connected circuit 60 for a U phase is a series-connected circuit of an upper arm formed of an IGBT (T1) with an antiparallel-connected diode D1, and a lower arm formed of a IGBT (T2) with an antiparallel-connected diode D2; a series-connected circuit 61 for a V phase is a series-connected circuit of an upper arm formed of an IGBT (T3) with an antiparallel-connected diode D3, and a lower arm formed of a IGBT (T4) with an antiparallel-connected diode D4; and a series-connected circuit 62 for a W phase is a series-connected circuit of an upper arm formed of an IGBT (T5) with an antiparallel-connected diode D5, and a lower arm formed of a IGBT (T6) with an antiparallel-connected diode D6.
Between the series connection point of the upper arm and lower arm and the DC neutral point potential M of the series-connected circuit for each phase is connected an AC switch in which is an antiseries-connected IGBT with an antiparallel-connected diode. That is, an AC switch, configured with the emitter of an IGBT module 63 formed of an IGBT 81 with an antiparallel-connected diode 82 connected to the emitter of an IGBT module 64 formed of an IGBT 83 with an antiparallel-connected diode 84, is connected between the series connection point and the DC power supply neutral point M of the series-connected circuit 60 for the U phase; an AC switch, configured with the emitter of an IGBT module 65 formed of an IGBT 85 with an antiparallel-connected diode 86 connected to the emitter of an IGBT module 66 formed of an IGBT 87 with an antiparallel-connected diode 88, is connected between the series connection point and the DC power supply neutral point M of the series-connected circuit 61 for the V phase; and, an AC switch, configured with the emitter of an IGBT module 67 formed of an IGBT 89 with an antiparallel-connected diode 90 connected to the emitter of an IGBT module 68 formed of an IGBT 91 with an antiparallel-connected diode 92, is connected between the series connection point and the DC power supply neutral point M of the series-connected circuit 62 for the W phase. The output of the series connection point of each of the series-connected circuits 60, 61, 62 is an AC output, and is connected to the load 74 via respective filtering inductors 71, 72, 73.
By using this circuit configuration, the series connection points of each of the series-connected circuits 60, 61, 62 can output the positive electrode potential P, negative electrode potential N, and neutral point potential M, for three-level inverter output. FIG. 14 shows an example of an output voltage (Vout) waveform. A feature compared with a two-level type inverter is the output of an AC voltage having three voltage levels with few lower-order harmonic components, so that the filtering inductors (output filters) 71 to 73 can be miniaturized.
Next, the three-level inverter of the prior art described in Patent Document 1 is explained using FIG. 15.
FIG. 15 is a diagram of the configuration of upper and lower arms for one phase, including an AC switch, of a three-level inverter; here FIG. 15(a) is a circuit diagram, and FIG. 15(b) is a perspective view of the semiconductor module.
The semiconductor module 40 shown in FIG. 15(b) accommodates an AC switch 53, in which two reverse blocking IGBTs 54 and 55 are antiparallel-connected, as shown in FIG. 15(a), and two IGBTs (T1 and T2).
FIG. 16 is a schematic cross-sectional view of the semiconductor module. In the semiconductor module 40, power semiconductor chips 43 (denoted by the symbols T1, T2, D1, D2, 54 and 55 in FIG. 15) are mounted on an insulating substrate 42 on a heat-dissipating metal base 41, metal terminals 44 leading to outside are exposed on the upper face of the package 45, and the interior of the package 45 is packed with resin 46.
This semiconductor module 40 is applied to a voltage-type three-level inverter. The semiconductor module 40 is formed of the first IGBT (T1) having a collector terminal C1 connected to the positive electrode terminal (P terminal) of the series-connected circuit 60 and having the diode D1 antiparallel-connected thereto, and the second IGBT (T2) having a collector connected to the emitter of the first IGBT (T1), an emitter terminal E2 connected to the negative electrode terminal (N terminal) of the series-connected circuit 60, and the diode D2 antiparallel-connected thereto.
The semiconductor module 40 is also formed of the AC switch 53, configured using the first reverse blocking IGBT 54 the collector of which is connected to the emitter of the first IGBT (T1) and the second reverse blocking IGBT 55 antiparallel-connected to the first reverse blocking IGBT 54.
The series-connected circuit 60 is configured using the first IGBT (T1) with the antiparallel-connected diode D1 and the second IGBT (T2), the positive electrode terminal (P terminal) of the series-connected circuit 60 is connected to the collector terminal C1 of the first IGBT, and the negative electrode terminal (N terminal) is connected to the emitter terminal E2 of the second IGBT (T2).
The AC switch 53 is configured using the first reverse blocking IGBT 54 and the second reverse blocking IGBT 55.
Further, the AC switch 53 is connected between the connection point E1C2 of the emitter of the first IGBT (T1) and the collector of the second IGBT (T2), and the intermediate potential terminal (M terminal) at an intermediate potential between the positive electrode terminal (P terminal) and negative electrode terminal (N terminal) of the series-connected circuit 60. The first IGBT (T1), second IGBT (T2), first reverse blocking IGBT 54 and second reverse blocking IGBT 55 are accommodated in a single package 45.
In this way, one upper and lower arm is accommodated in one package 45, and when three of these packages 45 are used to configure a three-level inverter, external wiring is simplified. Further, the wiring inductance of the three-level inverter can be reduced, and the device as a whole can be miniaturized.
Here, a reverse blocking IGBT is an IGBT having a reverse-direction breakdown voltage (reverse breakdown voltage) equal to the forward-direction breakdown voltage (forward breakdown voltage), and because the forward breakdown voltage and reverse breakdown voltage are equal, the device is sometimes called a symmetrical IGBT.
Further, an IGBT not having a reverse breakdown voltage refers to what is called an asymmetrical IGBT, the reverse breakdown voltage of which is much lower than the forward breakdown voltage. In an inverter circuit in which a reverse breakdown voltage is not applied, for example such an IGBT, the device is frequently used with an antiparallel-connected freewheeling diode. Normally, “IGBT” simply means an IGBT without a reverse breakdown voltage.
Further, Patent Documents 2 to 4 disclose so-called single units of a semiconductor module, in which two types of modules are prepared with the lead positions of the emitter terminals and collector terminals swapped, the two module types disposed in a row, and by connecting the emitter terminal of one module to the collector terminal of the other adjacent module, one upper and lower arm of an inverter are configured.
Patent Document 1: Japanese Patent Application Laid-open No. 2008-193779
Patent Document 2: Japanese Patent Application Laid-open No. H3-108749
Patent Document 3: Japanese Patent Application Laid-open No. H3-65065
Patent Document 4: Japanese Patent Application Laid-open No. H9-9644
However, when manufacturing a three-level inverter using the semiconductor module shown in FIG. 15, depending on the capacity of the three-level inverter, the IGBTs, reverse blocking IGBTs and other semiconductor elements incorporated within the module are changed. That is, in order to increase the capacity, the semiconductor element chip size may be changed, or parallel connections of IGBTs and reverse blocking IGBTs may be made. Thus when preparing three-level inverters with various capacities, dedicated semiconductor module packages 45 must be newly developed according to the IGBTs, reverse blocking IGBTs, and other semiconductor elements incorporated. Consequently in order to support a broad range of currents from tens of amperes to thousands of amperes, a number of packages must be newly prepared. Moreover, in order to support a broad range of breakdown voltages from hundreds of volts to over a thousand volts, a number of packages must be newly prepared.
There are also cases in which the first and second IGBTs (T1 and T2) and the first and second reverse blocking IGBTs 54 and 55 are used in separate packages 56a and 57 (see FIG. 17 and FIG. 19) to configure a three-level inverter.
FIG. 17 shows the configuration of inverter upper and lower arms for one phase; FIG. 17(a) is a circuit diagram, and FIG. 17(b) is a plane view of principal components of the semiconductor module. In the example shown, the three main terminals (E1C2, E2 and C1) are disposed in one row on the upper face of the package 56a. 
FIG. 18 is a diagram of the inner structure of the semiconductor module of FIG. 17. The E1C2 terminals at a and b are connected within the package 56a, and what is disposed above the package 56a is E1C2 a. 
FIG. 19 shows the configuration of an AC switch in which reverse blocking IGBTs are antiparallel-connected. FIG. 19(a) is a circuit diagram, and FIG. 19(b) is a plane view of the AC switch package.
The three-level inverter shown in FIG. 15 is configured combining semiconductor modules 47 of first and second IGBTs (T1 and T2) upper and lower arms (series-connected circuit 60) shown in FIG. 17 and FIG. 18, and AC switches 53 shown in FIG. 19 using first and second reverse blocking IGBTs 54 and 55. In this case, the package of a semiconductor module 47 shown in FIG. 17 is an existing package 56a, and is a normally used two-unit package accommodating an upper arm element and a lower arm element. On this existing package 56a are disposed the three main terminals (E1C2, C1 and E2).
However, the package 57 of the AC switch 53 shown in FIG. 19(b) differs from the internal wiring circuit configuration of the semiconductor module 47 shown in FIG. 17 and FIG. 18 in that there are two main terminals (the K terminal and L terminal), and so the package 56a of FIG. 17(b) cannot be used.
For this reason, a package 57 accommodating the first and second reverse blocking IGBTs 54 and 55 must be newly developed according to the current rating and voltage rating.
When manufacturing a three-level inverter, a new package must be developed both in cases where the semiconductor module 40 of FIG. 15 (new package 45) is used, and in cases where the semiconductor module 47 of FIG. 17 (existing package 56a) and the AC switch 53 of FIG. 19 (new package 57) are combined and used.
Further, Patent Documents 2 to 4 do not indicate that by changing semiconductor elements disposed in the interior using existing packages with external terminals in the same positions, two types of modules with the same package shape are formed, and the two types of modules are used to configure one upper and lower arm of a three-level inverter.